In recent years, along with the development of digital technology, functions of electronic devices such as portable information devices and information home appliances have been further improved. Therefore, demand for large capacity of a nonvolatile memory device, low write power, high speed writing/reading, and long product life is increasing.
In order to meet such a demand, more finely structured flash memory using an existing floating gate is being developed.
On the other hand, research and development of a nonvolatile memory device having a memory element including a so-called variable resistance memory element as a replacement for a flash memory has advanced. The variable resistance memory element is an element with characteristics such that the resistance value of the element changes according to an electrical signal and is maintained (nonvolatile) even when the electrical signal is turned off, and thus the element is capable of storing information by the resistance value change.
A typical variable resistance memory element includes an MRAM (Magnetic Random Access Memory), a PRAM (Phase Change Random Access Memory), a ReRAM (Resistance Random Access Memory), a SPRAM (Spin Transfer Torque Random Access Memory), and a CBRAM (Conductive Bridge Random Access Memory).
There is known a cross-point configuration as an example of configuration technique for a nonvolatile memory device using some of these variable resistance memory elements. In the cross-point configuration, a memory cell with two terminals is disposed at the position of each of three-dimensional cross-points of bit lines and word lines which are arranged perpendicularly, the memory cell being interposed between corresponding bit line and word line. The memory cell comprises a memory element including a single variable resistance memory element, or a variable resistance memory element and a switching element with two terminals such as a diode which are connected in series, one electrode of the memory element being connected to a word line, and the other electrode of the memory element being connected to a bit line. The cross-point configuration is, as its characteristics, suitable for large-scale integration in contrast to so-called 1T1R configuration, in which a variable resistance memory element is connected to a bit line via an access transistor with three terminals.
In the cross-point configuration, memory cells are disposed in an array (hereinafter referred to as a cross-point cell array). In the cross-point configuration, when a voltage is applied to corresponding bit line and word line to detect (read) the resistance value of a memory element included in a target memory cell, a current flows through not only the detection-target memory cell, but also other memory cells connected in parallel via vertical bit lines and word lines. The current which flows through other memory cells is referred to as a sneak current herein. The sneak current depends on a state (the resistance values and their distribution of the memory elements included in all memory cells in a cross-point cell array which contains a target memory cell to be detected) of data stored in a cross-point cell array, and thus the current detected at the time of reading always contains an offset current (=sneak current) which is not constant. The sneak current prevents accurate detection of the resistance value of a memory element included in a read-target memory cell.
By adopting a configuration in which a memory element includes a switching device and a variable resistance memory element connected in series, the sneak current can be reduced. However, the sneak current increases according to the scale of a cross-point cell array, thereby preventing production of large scale cross-point cell arrays.
Patent Literature (PTL) 1 discloses a storage device having a configuration which inhibits reduction in sensitivity of detection of the resistance value of a memory element included in a memory cell, which is caused by a sneak current, the reduction in sensitivity of detection being caused by a sneak current.